Via Pillar Flow in Innovus
Product Version: Innovus 18.x and above
September, 2018
Copyright Statement
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Via Pillar Flow in Innovus
Contents
Overview ...................................................................................................................... 4
Automatic Via Pillar Flow ............................................................................................. 5
Initialize DB .............................................................................................................. 5
Via Pillar PnR Flow .................................................................................................. 5
PostRoute Via Pillar Sizing and Timing-Driven ecoRoute ........................................ 6
Opportunistic Via Pillar ............................................................................................. 6
Data Preparation for Via Pillar Insertion....................................................................... 7
Via Pillar Definition in LEF ........................................................................................ 7
Cell Pin Via Pillar Association List ............................................................................ 8
Design Data Preparation .......................................................................................... 9
Via Pillar PnR Flow: Settings and Modes ............................................................... 11
How to Read the Report ......................................................................................... 11
ReportRouteTypeConstraints ................................................................................. 12
Advanced Usage .................................................................................................... 14
Recommended Flow .............................................................................................. 14
Clock Tree Synthesis ................................................................................................. 16
Sample Via Pillar Usage in Clock Tree .................................................................. 17
Alternate Flow: Via Pillar Optimization in postRoute .................................................. 19
Opportunistic Via Pillar Insertion ................................................................................ 20
How to Troubleshoot.................................................................................................. 23
Troubleshooting: Via Pillar Definition Errors in LEF ............................................... 23
Troubleshooting: No Via Pillar Insertion ................................................................. 24
Troubleshooting: MAXCELLEXTENSION Not Specified ........................................ 24
Troubleshooting: CUTCLASS Causing DRC Violation ........................................... 25
An Example in the Innovus flow ................................................................................. 25
Support ...................................................................................................................... 25
Feedback ................................................................................................................... 25
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Via Pillar Flow in Innovus
Overview
Via pillars are composed of stacked parallel wire segments on intermediate layers. Each
of the wire segments, except in the top layer, is connected above and below. The entire
via pillar structure looks like the Jenga tower in the popular game. The individual wire
segments are sometimes called fingers. There must be exactly one finger in the top
layer of the via pillars.
There are several benefits of adding via pillars in a design:
•
Connecting to multiple fingers of a pin
•
Replacing multi-cut via at DPT layers
•
Preventing EM violations
•
Improving timing performance
•
Adding to the robustness of slack
•
Improving utilization
Innovus provides a very flexible, easy-to-use, and effective automatic via pillar flow.
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Via Pillar Flow in Innovus
Automatic Via Pillar Flow
The following flow chart illustrates the Innovus via pillar flow:
Initialize DB: contains via pillar rule
definitions in LEF format; load via pillars vs.
cell pins associations
Via Pillar PnR Flow: effort level control
(EM, TD-low, TD-medium, TD-high).
Generates a PostRoute DB
PostRoute Via Pillar Sizing:
Upsize/add via pillars and timing-driven
ecoRoute focusing on creating optimal
output routing topology – better timing
Opportunistic Via Pillars: upgrade via
pillars or convert single cuts to via pillars w/o
creating DRCs – better slack quality
Initialize DB
To prepare for the via pillar flow, you must provide via pillar rule definitions in LEF. You
also need to associate library cell pins with a list of applicable via pillars. The details of
the via pillar rule definitions and the associate lists will be discussed in this document.
Via Pillar PnR Flow
Innovus provides an automatic PnR via pillar insertion flow. Innovus pillar optimization
has four effort modes EM-only, low, medium and high. Innovus GigaOpt automatically
evaluates timing tradeoffs and assigns the best via pillar rules to the instance pins (not
cell pins). Innovus NanoRoute implements the via pillars based on the assigned stack
via rules to instance pins or cell pins (if EM requirement exists).
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Via Pillar Flow in Innovus
PostRoute Via Pillar Sizing and Timing-Driven ecoRoute
In preRoute stages, the timing of design is not as accurate. As a result, the via pillar
flow faces the challeges of bridging the preRoute-postRoute timing correlation gap.
Once a postRoute database has been created, GigaOpt is able to more aggressively
upsize or add via pillars based on the more accurate postRoute timing. Furthermore,
timing-driven ecoRoute focuses on creating optimal routing topology on the output pin to
achieve better timing.
Opportunistic Via Pillar
With a post-routed design, the Innovus NanoRoute engine can scan for available tracks
around an output pin and add wire segments to either insert a new via pillar or upgrade
the current via pillar with more fingers at lower layers. Opportunistic via pillar
optimization is DRC clean by construction. There is no need to reroute the design after
this optimization.
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Via Pillar Flow in Innovus
Data Preparation for Via Pillar Insertion
For the via pillar flow to work correctly, the design data needs to be properly prepared.
Particularly, you need to prepare the via pillar definitions in the LEF file and prepare the
cell pin via pillar associate lists using the set_via_pillars commands.
Via Pillar Definition in LEF
Via pillars are defined either in the tech LEF file or in a separate LEF file. Via pillars are
created as STACKVIARULEs composed of individual STACKVIALAYERRULEs. Each
STACKVIALAYERRULE specifies:
•
Rule name
o Name of the STACKVIALAYERRULE
•
Via LAYER
o Layer of the via
•
Via CUTCLASS
o CUTCLASS of the via
•
Stack via row and column dimension
o ROWCOL: Number of vias (fingers) in y direction (ROW) and x direction
(COL)
•
xpitch and ypitch
o xpitch: The minimum number of tracks between adjacent vertical wires
o ypitch: The minimum number of tracks between adjacent horizontal wires
•
MAXCELLEXTENSION
o Maximum extension outside of cell boundary (by number of pitches) for via
pillar wire segments
The STACKVIARULE is composed of its individual STACKVIALAYERRULEs. The
ROWCOL configurations of adjacent STACKVIALAYERRULEs must be aligned
correctly. The top via pillar layer must be exactly one (1) finger.
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Via Pillar Flow in Innovus
The following is a sample definition of a via pillar from M1 to M4 (with 1, 3, 2, 1 fingers
in M1, M2, M3, M4, respectively.)
PROPERTYDEFINITIONS
# VPPERF_M1_M4_1_3_2_1
LIBRARY LEF58_STACKVIALAYERRULE STRING "
STACKVIALAYERRULE SVIA1 LAYER VIA1 CUTCLASS VSINGLECUT ROWCOL 3 1 XPITCH 2 YPITCH 3 MAXCELLEXTENSION 1 ;" ;
LIBRARY LEF58_STACKVIALAYERRULE STRING "
STACKVIALAYERRULE SVIA2 LAYER VIA2 CUTCLASS VSINGLECUT ROWCOL 3 2 XPITCH 4 YPITCH 3 MAXCELLEXTENSION 1 ;" ;
LIBRARY LEF58_STACKVIALAYERRULE STRING "
STACKVIALAYERRULE SVIA3 LAYER VIA3 CUTCLASS VSINGLECUT ROWCOL 1 2 XPITCH 4 YPITCH 2 MAXCELLEXTENSION 1 ;" ;
LIBRARY LEF58_STACKVIARULE STRING "
STACKVIARULE VPPERF_M1_M4_1_3_2_1 SVIA1 SVIA2 SVIA3 ;" ;
END PROPERTYDEFINITIONS
Let’s call above file as vp_rule.lef
Cell Pin Via Pillar Association List
You must associate cell pins with their applicable via pillars by using
set_via_pillars as follows:
set_via_pillars <pillar_list> -term <term> [-required <bool>]
The following are some examples of how set_via_pillars is generally used:
foreach cell [dbGet head.libCells.name -e AN2_NOM_D16*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M2_M4_1_2_1 VPPERF_M2_M5_1_2_2_1 VPPERF_M2_M9_1_2_2_2_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN2_NOM_D4*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M1_M4_1_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN2_NOM_D6*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M1_M4_1_2_2_1 VPPERF_M1_M5_1_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN2_NOM_D8*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M2_M4_1_2_1 VPPERF_M2_M5_1_2_2_1 VPPERF_M2_M9_1_2_2_2_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN3_NOM_D4*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M1_M4_1_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN3_NOM_D6*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M1_M4_1_2_2_1 VPPERF_M1_M5_1_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN3_NOM_D8*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M2_M4_1_2_1 VPPERF_M2_M5_1_2_2_1 VPPERF_M2_M9_1_2_2_2_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN4_NOM_D6*] {set_via_pillars -term $cell/Z -required 0
{VPPERF_M1_M4_1_2_2_1 VPPERF_M1_M5_1_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AN4_NOM_D8*] { set_via_pillars -term $cell/Z -required
0 {VPPERF_M2_M4_1_2_1 VPPERF_M2_M5_1_2_2_1 VPPERF_M2_M9_1_2_2_2_2_2_2_1} }
foreach cell [dbGet head.libCells.name -e AO211_NOM_D4*] { set_via_pillars -term $cell/Z required 0 {VPPERF_M1_M4_1_2_2_1} }
foreach cell [dbGet head.libCells.name -e AO21_NOM_D4*] { set_via_pillars -term $cell/Z -required
0 {VPPERF_M1_M4_1_2_2_1} }
foreach cell [dbGet head.libCells.name -e AO22_NOM_D4*] { set_via_pillars -term $cell/Z -required
0 {VPPERF_M1_M4_1_3_2_1 VPPERF_M1_M4_1_4_2_1} }
Let’s call above file as vp_association.tcl
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Via Pillar Flow in Innovus
The -required option specifies that an EM via pillar is required for the cell pin. The
EM via pillar is defined to be the smallest via pillar in the list (presumably satisfies the
EM requirement). Innovus can also upgrade the required EM via pillar to another
wider/taller via pillar specified in the association list if it provides a timing benefit over
the EM via pillar.
For secondary PG pins (being input pins by nature), the set_via_pillars command
does not work. This will be improved later. For now, use the following example:
dbSet [dbGet [dbGet head.libCells.name HDR27XSICWD1BWP300H11P57PDLVT -p
].pgTerms.name TVDD -p ].stackViaRequired 1
dbSet [dbGet [dbGet head.libCells.name HDR27XSICWD1BWP300H11P57PDLVT -p
].pgTerms.name TVDD -p ].stackViaList VPEM_M1_M4_14_1_3_1
Design Data Preparation
Design data must be prepared properly for the via pillar flow to work in Innovus.
Especially, it is important to make sure the vias are correctly generated by Innovus. To
achieve that, you need to follow a few guidelines.
If the library cell pins have multiple fingers and they must be connected (PROPERTY
LEF58 MUSTJOINALLPORTS exists), you must set the Tcl variable below. This
variable might become default soon, but it is a good idea to set it or check to make sure.
set mustjoinallports_is_one_pin 1
This Tcl var, if to be set, must be set before any library cell LEF file is parsed into
Innovus. In other words, it must be set before any initDesign or restoreDesign
command. Otherwise, inconsistency in DB might cause unexpected issues down the
flow.
If you use init_design to initialize the design data, it is recommended that the via
pillar LEF is included in the init_lef_file list before calling init_design:
setGenerateViaMode -auto true
setGenerateViaMode -advanced_rule true
...
setUserDataValue init_verilog $netlist
setUserDataValue init_lef_file “tlef.lef vp_rule.lef std.lef”
...
init_design
source vp_association.tcl
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Via Pillar Flow in Innovus
Notice that the following commands are required before init_design:
setGenerateViaMode –auto true
setGenerateViaMode –advanced_rule true
If setGenerateViaMode was skipped before init_design, you need to call
generateVias –advanced_rule after init_design:
...
setUserDataValue init_verilog $netlist
setUserDataValue init_lef_file “tlef.lef vp_rule.lef std.lef”
...
init_design
generateVias -advanced_rule
...
From a saved Innovus design, you can add the stack via rules by including the LEF file
in the .globals file in the saved design directory:
# in .globals
...
setUserDataValue init_lef_file “tlef.lef vp_rule.lef
std.lef”
...
You can also use loadLefFile after restoreDesign to read in the via pillar LEF file:
# start from a db without via pillar LEF
restoreDesign db/design.enc.dat design
loadLefFile vp_rule.lef
generateVias -advanced_rule
...
If you choose to use loadLefFile after restoreDesign, generateVias must be
called explicitly and immediately after loadLefFile. Some Innovus commands, when
invoked between loadLefFile and generateVias, might prevent the vias from
being generated correctly.
You are strongly encouraged to load all LEF files including via pillar definitions at the
beginning of the flow.
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Via Pillar Flow in Innovus
Via Pillar PnR Flow: Settings and Modes
There are four optModes for via pillar efforts:
•
•
•
•
setOptMode
setOptMode
setOptMode
setOptMode
-viaPillarEffort
-viaPillarEffort
-viaPillarEffort
-viaPillarEffort
none (EM-only mode)
low (default)
medium
high
Note: In Stylus Common User Interface (CUI), setOptMode -viaPillarEffort <>
maps to set_db opt_via_pillar_effort <>
Innovus GigaOpt applies different transformations in optimization stages for each
individual effort level.
The high effort level should be used with caution, especially for designs with high
utilization, due to possible over-assignment of via pillars.
Note that the via pillar definitions in the LEF file and the cell pin via pillar associate lists must be
successfully loaded in Innovus for viaPillarEffort modes to work correctly.
How to Read the Report
In the preRoute stage, you will find the following report in the place_opt_design
stage of the flow.
The report shows the number of instance pins that have stack via rules assigned to
them.
**** Begin NDR-Layer And Stack Via Rules Usage Statistics ****
Layer 5 has 24512 constrained nets
Layer 10 has 216 constrained nets
Stack Via Rule "VPPERF_M2_M9_1_2_2_2_2_2_2_1" is asserted on 141
instance pins, 0 cell pins
Stack Via Rule "VPPERF_M2_M5_1_2_2_1" is asserted on 16 instance pins,
0 cell pins
Stack Via Rule "VPPERF_M1_M4_1_4_2_1" is asserted on 2 instance pins,
0 cell pins
Stack Via Rule "VPPERF_M1_M4_1_3_2_1" is asserted on 26 instance pins,
0 cell pins
Stack Via Rule "VPPERF_M1_M4_1_2_2_1" is asserted on 460 instance
pins, 0 cell pins
Stack Via Rule "VPPERF_M2_M4_1_2_1" is asserted on 685 instance pins,
0 cell pins
**** End NDR-Layer And Stack Via Rules Usage Statistics ****
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Via Pillar Flow in Innovus
After the design has been routed, you can find the stack via implementation ratio in the
innovus.log or logv file (logv contains even more detailed information).
In this example, summation of numerators equals 1178. However, summation of
denominators equals 1208, which is more than 1204. This is because Innovus might
have attempted multiple via pillars on the same instance pin. Innovus attempts to insert
smaller via pillars if the currently assigned via pillar cannot be inserted successfully. If
an EM via pillar is required for the cell pin, at least the EM via pillar will be inserted even
with DRC violations. If an EM via pillar is not required, this instance pin could end up
with no via pillar at all if all via pillars of the cell pin fail to be inserted. Detailed failure log
can be found in the routing logv file.
ReportRouteTypeConstraints
After the design is routed, you can use the reportRouteTypeConstraints -svr
command. In CUI, command to be used is report_route_type_constraints stack_via_rule) to report detailed stack via rule constraints information. For each
stack via rule constraint, the following summaries are reported:
•
Routing cost
•
Number of constraints applied
•
Number of constraints implemented
•
Adherence ratio
•
Bottom-layer constraints
•
List of cells on which the stack via rule constraint was applied on driver
A sample stack via rule constraints report is shown below:
The list of cells on which a stack via rule constraint was applied on driver is also
reported:
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Via Pillar Flow in Innovus
Advanced Usage
If you are an advanced user, you can use the following commands to remove via pillar
associations on all library cell pins:
dbSet head.libCells.terms.stackViaRequired 0
dbSet head.libCells.terms.stackViaList {}
Note: CUI equivalent command is going to be as listed below:
set_db base_pin:<cell>/<pin> .stack_via_list
set_db base_pin:<cell>/<pin> .stack_via_required
For some designs, it is helpful to specify a keepout box for some cells or instances so
that there is more space to have via pillars inserted. Refer to the Innovus User Manual
for the usage of the specify_pg_keepout command.
Recommended Flow
It is recommended that you use low viaPillarEffort optMode in preRoute stages and
medium viaPillarEffort in postRoute optimization.
The following flow chart is a summary of the Innovus via pillar flow:
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Via Pillar Flow in Innovus
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Via Pillar Flow in Innovus
Clock Tree Synthesis
After clock trees are synthesized, it is often necessary to use via pillars for EM
prevention or timing improvement.
You can use the set_ccopt_property command to specify and overwrite the via
pillar settings for the instances and nets in the clock trees:
set_ccopt_property stack_via_rule
[-net_type trunk|leaf]
[-clock_tree clock_tree_name]
[-lib_pin cell_name/pin_name]
via_pillar_rule
Some sample usages are:
•
set_ccopt_property stack_via_rule –net_type trunk M1M4_1332
# CTS trunk nets use via pillar M1M4_1332.
•
set_ccopt_property stack_via_rule –clock_tree ck1 M1M4_1332
# All nets in ck1 use via pillar M1M4_1332.
•
set_ccopt_property stack_via_rule –lib_pin X/Y M1M4_1332
# All cell pins X/Y in clock trees use via pillar M1M4_1332.
Notice that only one via pillar rule can be specified using set_ccopt_property.
The options of set_ccopt_property can be mixed to provide a complex
configuration of via pillar settings for the clock trees in the design.
Notice that the settings by set_ccopt_property must be consistent with the cell pin
via pillar association lists specified by set_via_pillars. The via pillars might not get
implemented if there is any inconsistency between set_ccopt_property and
set_via_pillars.
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Via Pillar Flow in Innovus
Sample Via Pillar Usage in Clock Tree
The following is an example of how to set up a CTS flow using via pillars:
clk1
Top using NDR 3W2S
Cell:ViaPillar
BUFD12 : M1_M5_43321
BUFD10: M1_M5_43321
BUFD8: M1_M5_32221
Trunk using NDR 2W2S
Cell:ViaPillar
BUFD12 : M1_M4_4321
BUFD10: M1_M4_4321
BUFD8: M1_M4_3221
Leaf using NDR 1W2S
Cell:ViaPillar
BUFD12 : M1_M4_4321
BUFD10: (Default EM rule)
BUFD8: (Default EM rule)
create_route_type –name 3W2S –non_default_rule 3W2S
create_route_type –name 2W2S –non_default_rule 2W2S
create_route_type –name 1W2S –non_default_rule 1W2S
set_ccopt_property buffer_cells {BUFD8 BUFD10 BUFD12}
# For top tree:
set_ccopt_property route_type 3W2S –net_type top
set_ccopt_property stack_via_rule –lib_pin BUFD12/Z \
–net_type top M1_M5_43321
set_ccopt_property stack_via_rule –lib_pin BUFD10/Z \
–net_type top M1_M5_43321
set_ccopt_property stack_via_rule –lib_pin BUFD8/Z \
–net_type top M1_M5_33321
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Via Pillar Flow in Innovus
# For trunk tree:
set_ccopt_property route_type 2W2S –net_type top
set_ccopt_property stack_via_rule –lib_pin BUFD12/Z \
–net_type top M1_M4_4321
set_ccopt_property stack_via_rule –lib_pin BUFD10/Z \
–net_type top M1_M4_4321
set_ccopt_property stack_via_rule –lib_pin BUFD8/Z \
–net_type top M1_M4_3221
# For leaf tree:
set_ccopt_property route_type 1W2S –net_type leaf
set_ccopt_property stack_via_rule –lib_pin BUFD12/Z \
–net_type top M1_M4_4321
# Even if the user did not specify any rule for clock buffers,
CTS will still honor the minimal EM via pillar requirement.
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Via Pillar Flow in Innovus
Alternate Flow: Via Pillar Optimization in postRoute
Innovus provides an alternate flow in which via pillar optimization is applied on a routed
or postrouteopt-ed design that either has only EM via pillars inserted or no via pillars
inserted at all in preRoute stages. The benefits of using the postRoute alternate flow
include more stable and definite timing improvements and less changes to the existing
customer flow.
Note that even with this alternate flow, data preparation remains a critical issue. Refer to
the Design Data Preparation section content related to:
set mustjoinallports_is_one_pin 1
The LEF file that contains via pillar rules can be loaded later, but follow the data
preparation steps and guidelines mentioned previously. The via pillar association file
(library cell pins vs. via pillar lists) also needs to be sourced into Innovus.
During postRoute optimization, via pillars are added or upsized and timing-driven
routing creates optimal routing topology to improve timing:
This is enabled when the -viaPillarEffort optMode is medium:
setOptMode -viaPillarEffort mediumNote:
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Note: In CUI, setOptMode -viaPillarEffort <> maps to set_db
opt_via_pillar_effort <>
It is recommended that when the design requires EM via pillars, via pillar optimization
should start from the place_opt_design stage. If EM via pillars are not required, it is
preferred that via pillar optimization starts at postRoute stage in order to take advantage
of more accurate timing and achieve more stable and definite timing improvements.
Opportunistic Via Pillar Insertion
After the design is routed or postrouteopt-ed, NanoRoute can look for available tracks
around the instance pin to either add a new via pillar or upgrade the original smaller via
pillar to one with more fingers.
In the following example, there was no via pillar inserted on the z pin. In this case,
NanoRoute is able to find nearby available tracks to add an additional finger and create
a new via pillar VPPERF_M2_M4_1_2_1.
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The following example shows an upgrade from VPEM_M1_M4_3_1_2_1 to
VPPERF_M1_M4_3_2_2_1.
After opportunistic via pillar insertion, there is no need for ecoRoute; opportunistic via
pillar insertion is DRC clean by construction. Once again, make sure that data
preparation was completed in accordance with the procedures mentioned above.
You can perform opportunistic via pillar insertion by using the following command:
routeDesign –viaPillarOpt
You can specify a different cell pin via pillar association list for opportunistic via pillar
insertion than the other list used for PnR flow. This is not required, but optional.
Note: In CUI, routeDesign -viaPillarOpt maps to route_design via_pillar_opt
The mode below allows opportunistic via pillar insertion to go outside the cell areas
when searching for opportunities. By default, in low effort, the search radius is confined
by cell area. In medium effort, the search radius can reach outside the cell area by one
half of the row height. In high effort, it can reach outside the cell area by one full row
height. The higher the effort level, the more runtime is required to execute the
command. There is usually diminishing return in via pillar upgrades vs. increasing effort
level.
setNanoRouteMode –droutePostRouteViaPillarEffort
{low|medium|high}
Note: In CUI,
setNanoRouteMode -droutePostRouteViaPillarEffort <> maps to
set_db route_design_detail_post_route_via_pillar_effort <>
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Via Pillar Flow in Innovus
If runtime permits, Innovus recommends running multiple passes of routeDesign viaPillarOpt with increasing effort level; that is, {low -> medium -> high}. This
guarantees that more via pillars are inserted. If you go for high effort immediately, order
dependency might prevent some via pillars from being upgraded or added due to the
presence of other via pillars in its proximity.
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© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
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Via Pillar Flow in Innovus
How to Troubleshoot
There are many reasons why via pillar rules might not get implemented even when you
follow the recommended flow and procedures. This section discusses some common
questions about via insertion failures and the steps to identify the causes. In an ongoing
process, the Innovus R&D engineering team will actively look for ways to improve the
usability of the tool through better error messages and data checking to help identify
issues.
Troubleshooting: Via Pillar Definition Errors in LEF
Common errors when defining via pillars in LEF:
•
Adjacent STACKVIALAYERRULEs do not match:
...
STACKVIALAYERRULE SVIA2 LAYER VIA2 CUTCLASS VSINGLECUT ROWCOL 3 2 XPITCH 1
YPITCH 1 ;
...
STACKVIALAYERRULE SVIA3 LAYER VIA3 CUTCLASS VSINGLECUT ROWCOL 1 3 XPITCH 1
YPITCH 1 ;
...
In this example, the dimension of via array on VIA2 (3x2) is not compatible with
the dimension on VIA3 (1x3).
•
Topmost via pillar layer has more than one finger.
•
There are redundant and inconsistent redefinitions of STACKVIALAYERRULE or
STACKVIARULE in the same LEF file or across multiple LEF files.
•
Insufficient number of via pillars are defined in the LEF file. Matching via pillars
should be defined for layer assignment route layers to minimize redundant via
resistance and improve the via pillar insertion ratio.
Note that via pillar insertion does not honor the NDR rule on the net. NDR routing
connects to the top finger if NDR exists on this net. The NDR rule is not honored in the
intermediate layers of the via pillar.
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© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
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Via Pillar Flow in Innovus
Troubleshooting: No Via Pillar Insertion
Some common errors:
•
Check data preparation procedure (not necessarily ERRORs).
•
VIAINPINONLY property in LEF or NanoRouteMode prevents via pillar creation.
•
Instance pins under PG structure prevent DRC-free via pillar insertion.
•
The via pillar to be inserted is too large, and it goes beyond the cell area (see
below). This requires the MAXCELLEXTENSION attribute to be adjusted properly.
Troubleshooting: MAXCELLEXTENSION Not Specified
Metal pitches, especially in higher layers, might prevent via pillars from being
implemented because the pitch constraints in STACKVIALAYER rules might push the
via pillar fingers outside of the cell boundary. MAXCELLEXTENSION must be specified in
this case to allow the via pillar fingers to extend outside of the cell boundary.
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© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
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Via Pillar Flow in Innovus
Troubleshooting: CUTCLASS Causing DRC Violation
Make sure that the correct via CUTCLASS is specified in the STACKVIALAYERRULE
statements. Improperly selected CUTCLASS can cause DRC violations and prevent via
pillars from being implemented.
Innovus continues to print out proper and meaningful error messages to identify the root
cause of failure to insert via pillars. This is an ongoing process.
An Example in the Innovus flow
Specify following prior to init_design and include vp_rule.lef in lef list.
set mustjoinallports_is_one_pin 1
setGenerateViaMode -auto true
setGenerateViaMode -advanced_rule true
Specify following after init_design
Source vp_association.tcl
Specify following before place_opt_design
setOptMode -viaPillarEffort low
Specify following before postroute optimization
setOptMode -viaPillarEffort medium
Specify following after postroute optimization
reportRouteTypeConstraints -svr -file route_types.rpt
Support
Cadence Support Portal provides access to support resources, including an extensive
knowledge base, access to software updates for Cadence products, and the ability to
interact with Cadence Customer Support. Visit https://support.cadence.com.
Feedback
Email comments, questions, and suggestions to content_feedback@cadence.com.
Learn more at Cadence Support Portal - https://support.cadence.com
© 2019 Cadence Design Systems, Inc. All rights reserved worldwide.
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